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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hs-6617rh radiation hardened 2k x 8 cmos prom pinouts 24 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t24 top view 24 lead ceramic metal seal flatpack package (flatpack) mil-std-1835 cdfp4-f24 top view pin description a address input q data output e chip enable g output enable p program enable ( p hardwired to vdd, except during programming) 1 2 3 4 5 6 7 8 9 10 11 12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 16 17 18 19 20 21 22 23 24 15 14 13 vdd a9 p g a10 q7 q5 q4 q3 a8 e q6 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd vdd a8 a9 p g a10 e q7 q6 q5 q4 q3 2 3 4 5 6 7 8 9 10 11 12 1 24 23 22 21 20 19 18 17 16 15 14 13 features ? total dose 1 x 10 5 rad (si) ? latch-up free >1 x 10 12 rad (si)/s ? field programmable ? functionally equivalent to hm-6617 ? pin compatible with intel 2716 ? low standby power 1.1mw max ? low operating power 137.5mw/mhz max ? fast access time 100ns max ? ttl compatible inputs/outputs ? synchronous operation ? on chip address latches ? three-state outputs ? nicrome fuse links ? easy microprocessor interfacing ? military temperature range -55 o c to +125 o c description the intersil hs-6617rh is a radiation hardened 16k cmos prom, organized in a 2k word by 8-bit format. the chip is manufactured using a radiation hardened cmos process, and is designed to be functionally equivalent to the hm-6617. synchronous circuit design techniques combine with cmos processing to give this device high speed performance with very low power dissipation. on chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structure, such as the hs-80c85rh or hs-80c86rh. the output enable control ( g) simpli?es microprocessor system interfacing by allowing output data bus control, in addition to, the chip enable control. synchronous operation of the hs-6617rh is ideal for high speed pipe-lined architecture systems and also in synchronous logic replacement functions. applications for the hs-6617rh cmos prom include low power microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement. ordering information part number temperature range package hs1-6617rh-q -55 o c to +125 o c 24 lead sbdip hs1-6617rh-8 -55 o c to +125 o c 24 lead sbdip hs1-6617rh/sample 25 o c 24 lead sbdip hs1-6617rh/proto -55 o c to +125 o c 24 lead sbdip hs9-6617rh-q -55 o c to +125 o c 24 lead flatpack HS9-6617RH-8 -55 o c to +125 o c 24 lead flatpack hs9-6617rh/sample 25 o c 24 lead flatpack hs9-6617rh/proto -55 o c to +125 o c 24 lead flatpack august 1995 spec number 518742 file number 3033.3 db na
2 hs-6617rh functional diagram truth table e g mode 0 0 enabled 0 1 output disabled 1 x disabled msb lsb 16 128 x 128 matrix gated row decoder latched address register register latched address gate column decoder programming, & data output control 16 16 16 16 16 16 16 e e e 8 a 4 a 4 e 8 1 of 8 7a 7 a 128 msb lsb p e g a10 a9 a8 a7 a5 a4 a6 a3 a2 a1 a0 q0 - q7 all lines positive logic: active high three state buffers: output active address latches & gated decoders: p = hardwired to vdd except during programming latch on falling edge of e gate on falling edge of g a high spec number 518742
3 speci?cations hs-6617rh absolute maximum ratings reliability information supply voltage ( all voltages reference to device gnd) . . . . +7.0v input or output voltage applied for all grades. . . . . . . . . . . . . . . . . gnd-0.3v to vdd+0.3v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance q ja q jc sidebraze dip package . . . . . . . . . . . . . 40 o c/w 6 o c/w ceramic flatpack package . . . . . . . . . . . 60 o c/w 4 o c/w maximum package power dissipation at +125 o c sidebraze dip package . . . . . . . . . . . . . . . . . . . . . . . . . . 1.251w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.83w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sidebraze dip package . . . . . . . . . . . . . . . . . . . . . . . .25.0mw/c ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . .16.7mw/c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating supply voltage range (vdd) . . . . . . . . . +4.5v to +5.5v operating temperature range (t a ) . . . . . . . . . . . . -55 o c to +125 o c input low voltage (vil). . . . . . . . . . . . . . . . . . . . . . . . . .0v to +0.8v input high voltage (vih) . . . . . . . . . . . . . . . . . . . . . . . +2.4v to vdd table 1. dc electrical performance characteristics device guaranteed and 100% tested. parameter symbol (notes 1, 2) conditions group a subgroups temperature limits units min max high level output voltage voh1 vdd = 4.5v, io = -2.0ma 1, 2, 3 -55 o c t a +125 o c 2.4 - v low level output voltage vol vdd = 4.5v, io = 4.8ma 1, 2, 3 -55 o c t a +125 o c - 0.4 v high impedance output leakage current ioz vdd = 5.5v, g = 5.5v, vi/o = gnd or vdd 1, 2, 3 -55 o c t a +125 o c -10.0 10.0 m a input leakage current ii vdd = 5.5v, vi = gnd or vdd, p not tested 1, 2, 3 -55 o c t a +125 o c -1.0 1.0 m a standby supply current iddsb vdd = 5.5v, io = 0ma, vi = vdd or gnd 1, 2, 3 -55 o c t a +125 o c - 200 m a operating supply current iddop vdd = 5.5v, g = gnd, (note 3), f = 1mhz, io = 0ma, vi = vdd or gnd 1, 2, 3 -55 o c t a +125 o c - 25 ma functional test ft vdd = 4.5v (note 4) 7, 8a, 8b -55 o c t a +125 o c- - - notes: 1. all voltages referenced to device gnd. 2. all tests performed with p hardwired to vdd. 3. typical derating = 20ma/mhz increase in iddop. 4. tested as follows: f = 1mhz, vih = 2.4v, vil = 0.8v, ioh = -1ma, iol = +1ma, voh 3 1.5v, vol 1.5v. table 2. ac electrical performance characteristics device guaranteed and 100% tested. parameters symbol (notes 1, 2, 3) conditions group a subgroups temperature limits units min max address access time tavqv vdd = 4.5v and 5.5v (note 4) 9, 10, 11 -55 o c t a +125 o c - 120 ns output enable access time tglqv vdd = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c - 50 ns chip enable access time telqv vdd = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c - 100 ns address setup time tavel vdd = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c20 - ns spec number 518742
4 speci?cations hs-6617rh address hold time telax vdd = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c25 - ns chip enable low width teleh vdd = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c 120 - ns chip enable high width tehel vdd = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c40 - ns read cycle time telel vdd = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c 160 - ns notes: 1. all voltages referenced to device gnd. 2. ac measurements assume transition time 5ns; input levels = 0.0v to 3.0v; timing reference levels = 1.5v; output load = 1 ttl equivalent load and cl 3 50pf. 3. all tests performed with p hardwired to vdd. 4. tavqv = telqv + tavel. table 3. electrical performance characteristics, ac and dc parameters symbol (note 2) conditions notes temperature limits units min max input capacitance cin vdd = open, f = 1mhz 1, 3 t a = +25 o c - 10 pf i/o capacitance ci/o vdd = open, f = 1mhz 1, 3 t a = +25 o c - 12 pf chip enable time telqx vdd = 4.5v and 5.5v 3 -55 o c t a +125 o c5 - ns output enable time tglqx vdd = 4.5v and 5.5v 3 -55 o c t a +125 o c5 - ns chip disable time tehqz vdd = 4.5v and 5.5v 3 -55 o c t a +125 o c - 50 ns output disable time tghqz vdd = 4.5v and 5.5v 3 -55 o c t a +125 o c - 50 ns output high voltage voh2 vdd = 4.5v, io = 100 m a 3 -55 o c t a +125 o c vdd- 0.5v -v notes: 1. all measurements referenced to device gnd. 2. all tests performed with p hardwired to vdd. 3. the parameters listed are controlled via design or process parameters and are not directly tested. these parameters are chara cterized upon initial design and after design or process changes which would affect these characteristics. table 4. post 100k rad ac and dc electrical performance characteristics note: all ac and dc parameters are tested at the +25 o c pre-irradiation limits. table 2. ac electrical performance characteristics (continued) device guaranteed and 100% tested. parameters symbol (notes 1, 2, 3) conditions group a subgroups temperature limits units min max spec number 518742
5 hs-6617rh table 5. burn-in delta parameters (+25 o c) parameter symbol delta limits standby supply current iddsb 10 m a input leakage current ioz 1 m a ii 100na output low voltage vol 60mv output high voltage voh 400mv table 6. applicable subgroups conformance group mil-std-883 method group a subgroups tested for -q recorded for -q tested for -8 recorded for -8 initial test 100% 5004 1, 7, 9 1 (note 2) 1, 7, 9 interim test 100% 5004 1, 7, 9, d 1, d (note 2) 1, 7, 9 pda 100% 5004 1, 7, d - 1, 7 final test 100% 5004 2, 3, 8a, 8b, 10, 11 - 2, 3, 8a, 8b, 10, 11 group a (note 1) sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 - 1, 2, 3, 7, 8a, 8b, 9, 10, 11 subgroup b5 sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, d 1, 2, 3, d (note 2) - subgroup b6 sample 5005 1, 7, 9 - - group c sample 5005 - - 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group d sample 5005 1, 7, 9 - 1, 7, 9 group e, subgroup 2 sample 5005 1, 7, 9 - 1, 7, 9 notes: 1. alternate group a testing in accordance with mil-std-883 method 5005 may be exercised. 2. table 5 parameters only spec number 518742
6 hs-6617rh spec number 518742 intersil space level product flow -q wafer lot acceptance (all lots) method 5007 (includes sem) gamma radiation veri?cation (each wafer) method 1019, 2 samples/wafer, 0 rejects 100% die attach (note 1) 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a csi and/or gsi pre-cap (note 8) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind, method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in 1, condition a or b, 72 hours min, +125 o c min, method 1015 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% pda 1, method 5004 (note 2) 100% dynamic burn-in, condition d, 240 hours, +125 o c or equivalent, method 1015 100% interim electrical test 2(t2) 100% delta calculation (t0-t2) 100% pda 2, method 5004 (note 2) 100% final electrical test 100% fine/gross leak, method 1014 100% radiographic (x-ray), method 2012 (note 3) 100% external visual, method 2009 sample - group a, method 5005 (note 4) sample - group b, method 5005 (notes 5 and 6) sample - group d, method 5005 (notes 6 and 7) 100% data package generation (note 9) csi and/or gsi final (note 8) notes: 1. epoxy or silver glass die attach shall be permitted. 2. failures from subgroup 1, 7 and deltas are used for calculating pda. the maximum allowable pda = 5% with no more than 3% of t he failures from subgroup 7. 3. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 4. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 5. qci subgroup b5 samples are programmed with a checkerboard pattern before life test and pattern tested after life test. there fore, the subgroup b5 samples must be considered destruct samples and cannot be shipped as ?ight quantity. 6. group b and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should i nclude separate line items for group b test, group samples, group d test and group d samples. 7. group d generic data, as de?ned by mil-i-38535, is optional and will not be supplied unless required by the p.o. when require d, the p.o. should include a separate line item for group d generic data. generic data is not guaranteed to be available and is theref ore not available in all cases. 8. csi and/or gsi inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should include separate line items for csi precap inspection, csi final inspection, gsi precap inspection, and/or gsi final inspection. 9. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). ? wafer lot acceptance report (method 5007). includes reproductions of sem photos with percent of step coverage. ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? x-ray report and ?lm. includes penetrometer measurements. ? screening, electrical, and group a attributes (screening attributes begin after package seal). ? lot serial number sheet (good units serial number and lot number). ? variables data (all delta operations). data is identi?ed by serial number. data header includes lot number and date of test. ? group b and d attributes and/or generic data is included when required by the p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of the data book. the certi?cate of conformanc e is signed by an authorized quality representative.
7 hs-6617rh spec number 518742 intersil space level product flow -8 gamma radiation veri?cation (each wafer) method 1019, 2 samples/wafer, 0 rejects 100% die attach (note 1) periodic- wire bond pull monitor, method 2011 periodic- die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition b csi and/or gsi pre-cap (note 7) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% external visual 100% initial electrical test 100% dynamic burn-in, condition d, 160 hours, +125 o c or equivalent, method 1015 100% interim electrical test 100% pda, method 5004 (note 2) 100% final electrical test 100% fine/gross leak, method 1014 100% external visual, method 2009 sample - group a, method 5005 (note 3) sample - group b, method 5005 (note 5) sample - group c, method 5005 (notes 4, 5 and 6) sample - group d, method 5005 (notes 5 and 6) 100% data package generation (note 8) csi and/or gsi final (note 7) notes: 1. epoxy or silver glass die attach shall be permitted. 2. failures from subgroup 1, 7 and deltas are used for calculating pda. the maximum allowable pda = 5%. 3. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 4. qci group c samples are programmed with a checkerboard pattern before life test and pattern tested after life test. therefore , the group c samples must be considered destruct samples and cannot be shipped as ?ight quantity. 5. group b, c and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. shoul d include separate line items for group b test, group c test, group c samples, group d test and group d samples. 6. group c and/or group d generic data, as de?ned by mil-i-38535, is optional and will not be supplied unless required by the p. o. when required, the p.o. should include a separate line item for group c generic data and/or group d generic data. generic data is no t guar- anteed to be available and is therefore not available in all cases. 7. csi and/or gsi inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should include separate line items for csi precap inspection, csi final inspection, gsi precap inspection, and/or gsi final inspection. 8. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? screening, electrical, and group a attributes (screening attributes begin after package seal). ? group b, c and d attributes and/or generic data is included when required by the p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of the data book. the certi?cate of conformanc e is signed by an authorized quality representative.
8 hs-6617rh timing waveform figure 1. read cycle valid data telqx tglqx 1.5v 1.5v tghqz tglqv 1.5v 1.5v tehqz 1.5v 1.5v teleh tehel telqv telax tavel telel valid address 1.5v 1.5v tavqv valid addresses ts 3.0v 0v 0v 3.0v 0v 3.0v addresses data output g e q0 - q7 spec number 518742
9 burn-in circuits hs-6617rh 24 lead sbdip and flatpack static configuration notes: 1. vdd = 6.0v 0.5v 2. c1 = 0.01 m f (min) 3. all resistors = 47k w 5% 4. y = 2.7v 10% hs-6617rh 24 lead sbdip and flatpack dynamic configuration notes: 1. vdd = 6.0v 0.5v 2. vih = 4.5v 10% 3. vil = 0.8v (max) 4. c1 = 0.01 m f (min) 5. all resistors = 47k w 5% 6. f0 = 100khz 10%, 40 - 60% duty cycle 7. f1 = f0/2 . . . f13 = f12/2 8. y = 2.7v 10% irradiation circuit hs-6617rh 24 lead flatpack notes: 1. power supply: vdd = 5.5v 2. all registors = 47k w 3. pin 18 is toggled from vss to vdd then back to vss and held at vss during irradiation. a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd vdd a8 q3 a9 a10 q7 q6 q5 q4 e g p vdd c1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd yy a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd vdd a8 q3 a9 a10 q7 q6 q5 q4 e g p f9 c1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vdd f11 f12 vdd f1 f13 f0 f10 f8 f7 f6 f5 f4 f3 yy load = vdd vss 47k w 47k w 16 17 18 19 20 21 22 23 24 15 14 13 load load load load load 1 2 3 4 5 6 7 8 9 10 11 12 vdd load load load nc nc nc toggle (note 3) hs-6617rh spec number 518742
10 hs-6617rh metallization topology die dimensions: 164 x 250 x 19 1mils metallization: type: silicon-aluminum thickness: 13k ? 2k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: 1 x 10 5 a/cm 2 substrate potential: vdd metallization mask layout hs-6617rh a2 (6) a1 (7) a0 (8) q0 (9) q1 (10) q2 (11) gnd (12) q3 (13) q4 (14) q5 (15) q6 (16) q7 (17) (20) g (19) a10 (18) e (5) a3 (4) a4 (3)a5 (2) a6 (1) a7 (24)vdd (23) a8 (22) a9 (21) p spec number 518742
the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 11 semiconductor background information hs-6617rh programming programming specifications parameter symbol min typ max units notes input "0" vil 0.0 0.2 0.8 v voltage "1" vih vdd-2 vdd vdd+0.3 v 6 programming vdd vddprog 10.0 10.0 10.0 v 2 operating vdd vdd1 4.5 5.5 5.5 v special verify vdd2 4.0 - 6.0 v 3 delay time td 1.0 1.0 - m s rise time tr 1.0 10.0 10.0 m s fall time tf 1.0 10.0 10.0 m s chip enable pulse width tehel 50 - - ns address valid to chip enable low time tavel 20 - - ns chip enable low to output valid time telqv - - 120 ns programming pulse width tpw 90 100 110 m s4 input leakage at vdd = vddprog tip -10 +1.0 10 m a data output current at vdd = vddprog iop - -5.0 -10 ma output pull-up resistor rn 5 10 15 k w 5 ambient temperature t a -25- o c notes: 1. all inputs must track vdd (pin 24) within these limits. 2. vddprog must be capable of supplying 500ma. vddprog power supply tolerence 3% (max.) 3. see steps 22 through 29 of the programming algorithm. 4. see step 11 of the programming algorithm. 5. all outputs should be pulled up to vdd through a resistor of value rn. 6. except during programming (see programming cycle waveforms). hs-6617rh 2k x 8 cmos prom spec number 518742 design information july 1995
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 12 hs-6617rh background information programming the hs-6617 cmos prom is manufactured with all bits containing a logical zero (output low). any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. to accomplish this, a programmer can be built that meets the speci?cations shown, or use of an approved commercial programmer is recommended. programming sequence of events 1. apply a voltage of vdd1 to vdd of the prom. 2. read all fuse locations to verify that the prom is blank (output low). 3. place the prom in the initial state for programming: e = vih, p = vih, g = vil. 4. apply the correct binary address for the word to be programmed. no inputs should be left open circuit. 5. after a delay of td, apply voltage of vil to e (pin 18) to access the addressed word. 6. the address may be held through the cycle, but must be held valid at least for a time equal to td after the falling edge of e. none of the inputs should be allowed to float to an invalid logic level. 7. after a delay of td, disable the outputs by applying a voltage of vih to g (pin 20). 8. after a delay of td, apply voltage of vil to p (pin 21). 9. after delay of td, raise vdd (pin 24) to vddprog with a rise time of tr. all outputs at vih should track vdd within vdd-2.0v to vdd+0.3v. this could be accomplished by pulling outputs at vih to vdd through pull-up resistors of value rn. 10. after a delay of td, pull the output which corresponds to the bit to be programmed to vil. only one bit should be programmed at a time. 11. after a delay of tpw, allow the output to be pulled to vih through pull-up resistor rn. 12. after a delay of td, reduce vdd (pin 24) to vdd1 with a fall time of tf. all outputs at vih should track vdd with vdd-2.0v to vdd+0.3v. this could be accomplished by pulling outputs at vih to vdd through pull-up resis- tors of value rn. 13. apply a voltage of vih to p (pin 21). 14. after a delay of td, apply a voltage of vil to g (pin 20). 15. after a delay of td, examine the outputs for correct data. if any location verifies incorrectly, it should be considered a program- ming reject. 16. repeat steps 3 through 15 for all other bits to be programmed in the prom. post-programming veri?cation 17. place the prom in the post-programming verification mode: e = vih, g = vil, p = vih, vdd (pin 24) = vdd1. 18. apply the correct binary address of the word to be verified to the prom. 19. after a delay of td, apply a voltage of vil to e (pin 18). 20. after a delay of td, examine the outputs for correct data. if any location fails to verify correctly, the prom should be considered a programming reject. 21. repeat steps 17 through 20 for all possible programming locations. post-programming read 22. apply a voltage of vdd2 = 4.0v to vdd (pin 24). 23. after a delay of td, apply a voltage of vih to e (pin 18). 24. apply the correct binary address of the word to be read. 25. after a delay of tavel, apply a voltage of vil to e (pin 18). 26. after a delay of telqv, examine the outputs for correct data. if any location fails to verify correctly, the prom should be consid- ered a programming reject. 27. repeat steps 23 through 26 for all address locations. 28. apply a voltage of vdd2 = 6.0v to vdd (pin 24). 29. repeat steps 23 through 26 for all address locations. spec number 518742
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 13 hs-6617rh figure 2. hs-6617rh programming cycle figure 3. hs-6617rh post programming verify cycle valid tehel valid programming verify read data vih vil vddprog vih vil vih vil vddprog vih vil vddprog vdd gnd vddprog a g p vdd q e vih/voh vil/vol td td td td tr td tpw td tf td valid vih vil vih vil vdd voh vol a q tavel tehel tehel tehel td telqv telqv telqv read read read 6.0v 5.0v 4.0v 0.0v e td spec number 518742
14 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hs-6617rh spec number

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